General Information

Req #
WD00061101
Career area:
Hardware Engineering
Country/Region:
India
State:
Karnataka
City:
BANGALORE
Date:
Friday, February 2, 2024
Working time:
Full-time
Additional Locations
* India

Why Work at Lenovo

 We are Lenovo. We do what we say. We own what we do. We WOW our customers. 

Lenovo is a US$62 billion revenue global technology powerhouse, ranked #171 in the Fortune Global 500, employing 77,000 people around the world, and serving millions of customers every day in 180 markets. Focused on a bold vision to deliver smarter technology for all, Lenovo has built on its success as the world’s largest PC company by further expanding into growth areas that fuel the advancement of ‘New IT’ technologies (client, edge, cloud, network, and intelligence) including server, storage, mobile, software, solutions, and services. 

This transformation together with Lenovo’s world-changing innovation is building a more inclusive, trustworthy, and smarter future for everyone, everywhere. To find out more visit https://www.lenovo.com, and read about the latest news via our StoryHub. 

Description and Requirements

This role is for a Component Library engineer in the Lenovo Datacenter Product Group (DCG), based out of Bangalore, Karnataka. This role is core to the Server Development organization in providing the component library necessary to design and deliver innovative server designs across DCG.  This librarian will be on a team responsible for the creation and maintenance of Printed Circuit Board (PCB) component models including logic, footprints padstack and component metadata, while ensuring they are compliant with JEDEC and IPC industry standards.  This role will also include Physical Design activity to support PCB component placement, routing feasibility studies, constraint rules and implementing DFT/DFM rules.  Engagement with engineering, supplier quality teams and card manufacturing will be required to keep the library compliant to deliver new and existing server designs with the highest quality to maintain exceptional reliability to our customers.  This candidate will be an active member of the development team that is highly motivated to engage, understand and solve the technical challenges of today and shape the server designs of tomorrow.

Expected responsibilities will include:

  • Creation and maintenance of PCB component models using the Cadence EDM Library development tools.
  • 7+ Yeras of experience
  • Fully Document all Library supported processes & specifications
  • Support Component Revision Control
  • Work in Cadence EDM Component Request/Tracking system
  • Work with Cadence Application Engineers to debug Library and Design Issues
  • Daily Interface with all World Wide Engineering Customers & MCAD Engineers as Project/Program needs arise
  • Interface with Component Engineering and Supply Chain Team
  • Experience extracting data centric attributes from vendor supplied spreadsheets for automated symbol development and verification

Required skills:

  • Expertise in Component Schematic and Printed Circuit Board (PCB) Library creation using Cadence Allegro Library Development tools, version 17.2 or higher. Specific Library tools experience includes:
    • EDM Project Manager
    • Allegro Library Manager
    • Allegro PCB Librarian Expert
    • Allegro Part Developer
    • Allegro ECAD/MCAD Library Creator
    • Allegro PCB Editor
    • Allegro Design Entry (Concept)
  • 7+ years’ experience with ECAD PCB Library and Layout Development
  • Leverage and support Importing and validating 3D Step models (vendor supplied)
  • Interpret Manufactures’ component Datasheets
  • Understand electronic symbols and how they interconnect to each other.
  • Familiarity with PLM systems i.e. PTC Windchill/PLM
  • Industry Standards (IPC, IEEE, JEDEC, Corporate) Padstack and Footprint and Schematic Symbol  Development Expertise
  • Layout Design Rule Constraints using Cadence Constraint Manager

Additional preferred skills:

  • Familiarity of PCB design processes to analyze library change requests to recommend best course of action to implement library changes
  • Familiarity with the Cadence SPB design flow, schematic to board netlisting flow
  • Ability to debug Cadence Design Entry HDL netlist errors as part of library development process

Additional Locations
* India
* India